The present invention is directed integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for monitoring a low energy dose implantation process for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to a variety of devices such as dynamic random access memory devices, static random access memory devices (SRAM), application specific integrated circuit devices (ASIC), microprocessors and microcontrollers, Flash memory devices, and others.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed.
An example of a semiconductor process that is important to make smaller and smaller devices is ion implantation for shallow junction MOS devices. Shallow junction MOS devices often require low energies but high impurity doses. Certain types of implantation such as boron use implant energies of 2 keV and possibly less. Such implant energies and doses are often difficult to monitor accurately. Here, measurement of implant depth and other parameters are often difficult or impossible using conventional techniques. In certain conventional techniques, screen oxides are formed on wafers before implantation. Low energy impurities often become trapped in the oxide layer and do not even reach the underlying silicon material. Resistance measurements of such oxide coated waters cannot be made accurately. Alternatively, bare silicon wafers are also implanted with impurities. These wafers often out diffuse the implanted impurities, which cannot be measured to any degree of accuracy. Accordingly, it is difficult to accurately monitor low energy implants for the manufacture of semiconductor devices.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.